Since the invention of the integrated circuit, the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surfaces of the semiconductor substrates in the semiconductor wafers. Although dramatic improvement in lithography has resulted in considerable improvement in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limit comes from the significant increase in the number and the length of interconnections between devices as the number of devices increases. When the number and the length of interconnections increase, both circuit RC delay and power consumption increase.
Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the above-discussed limitations. In a typical 3D integrated circuit formation process, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Through-silicon vias may then be used to interconnect devices on the two wafers.
Conventional methods for bonding two wafers include adhesive bonding, direct copper bonding and direct oxide bonding. In the commonly used direct copper bonding, each of the two wafers has copper pads exposed on the surfaces of the wafers, and the two wafers are bonded by applying a high pressure, so that the copper pads are bonded together.
Due to the customized circuit requirements, some bond pads need to be large. These large bond pads suffer from problems. FIG. 1 illustrates the bonding of two chips through large bond pads. Chip 2 includes large bond pad 4, chip 6 includes large bond pad 8. Bond pads 4 and 8 are bonded through direct copper bonding. In the formation of bond pads 4 and 8, chemical mechanical polish (CMP) processes typically involved. However, since bond pads 4 and 8 are large, the respective regions of bond pads 4 and 8 are pattern-dense regions. As a result, during the CMP processes for forming large bond pads 4 and 8, a dishing effect occurs, which causes the center regions of bond pads 4 and 8 to be polished more than the edge regions.
It is observed from FIG. 1 that the dishing effect may cause various problems. First, the reliability of the bonding is adversely affected. With the dishing effect, only small portions of bond pads 4 and 8 are bonded to each other, and hence the bonding is less reliable. Second, the current that may flow through the bonded area is reduced due to the reduced bond area. These problems defeat the purpose of designing large bond pads, and hence need to be addressed.